1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices having trench-type device isolation structure.
2. Description of the Background Art
In manufacturing semiconductor integrated circuits, device isolation regions must be formed to prevent electric interference among devices during operation so that the individual devices can be controlled perfectly independently. Methods for forming the device isolation regions include the well-known trench isolation method, for which many improvements have been proposed. This trench isolation method is generally used for a wide variety of LSIs.
In the trench isolation method, a trench (groove) formed on a substrate is filled with insulator to electrically isolate adjacent devices, such as MOS transistors. Since this method can maintain required electric isolating capability even with miniaturized devices, it is considered to be an indispensable device isolation method for further miniaturization of semiconductor integrated circuits.
FIGS. 15 to 21 are sectional views showing a conventional method of forming trench isolation. As shown in FIG. 15, a stacked mask layer 2 made of silicon oxide film and silicon nitride film is deposited by a CVD method all over a single-crystal semiconductor substrate 1 (which may be simply referred to as a "substrate" hereinafter).
Subsequently, as shown in FIG. 16, a resist mask 3 is formed with openings for formation of trenches in given areas. Next, as shown in FIG. 17, an etching is applied by using the resist mask 3 as a mask to form a plurality of trenches 4, and then the resist mask 3 is removed as shown in FIG. 18.
Next, as shown in FIG. 19, a silicon oxide film 5 is deposited in the trenches 4 and on the stacked mask layer 2 by using an HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method.
Next, as shown in FIG. 20, the entire surface is polished by using a chemical mechanical polishing (CMP) method to remove the silicon oxide film 5 on the stacked mask layer 2 and part of the surface of the silicon oxide film 5 in the trenches 4 for planarization.
Then, as shown in FIG. 21, the silicon nitride film part of the stacked mask layer 2 is removed by etching using thermal phosphoric acid and the silicon oxide film part of the stacked mask layer 2 is removed by wet etching using HF, and a trench isolation structure with the silicon oxide film 5 buried in the trenches 4 is thus completed.
Subsequently, desired semiconductor devices are formed on the semiconductor substrate 1 in the plurality of device formation areas AS which are trench-isolated by the silicon oxide film 5 buried in the trenches 4 to fabricate semiconductor integrated circuit devices.
During formation of the trenches 4, it is not essential to etch the stacked mask layer 2 and the semiconductor substrate 1 by using the resist mask 3. In a widely used method, the stacked mask layer 2 is patterned by using the resist mask 3 and then the patterned stacked mask layer 2 is used as a mask for etching the semiconductor substrate 1. Although not shown in the diagrams, an inner-wall oxide film may be formed inside the trenches (grooves) formed in the substrate.
The conventional trench isolation method shown in FIGS. 15 to 21 merely applies a chemical mechanical polishing after deposition of the silicon oxide film 5, however, and it is difficult to accomplish the polishing by using a CMP method so that the silicon oxide film 5 (see FIG. 22) is completely removed in raised areas such as the relatively large flat area A1 with the silicon oxide film 5 in the trenches 4 remaining unremoved.
That is to say, while applying the CMP in such a manner that the silicon oxide film 5 in the trenches 4 certainly remains tends to allow the silicon oxide film 5 to remain as a residue 5a after polishing as shown in FIG. 23, applying the CMP so as to certainly prevent the residue 5a after polishing tends to cause over-polishing to the trenches 4 and intervals between the trenches 4 as shown in FIG. 24, which may result in polished injuries 5b.
As described above, the conventional trench isolation method shown in FIGS. 15 to 21 has the problem that it is difficult to uniformly polish the entire substrate surface.
Accordingly, an improvement of the trench isolation method has been accomplished as shown in FIGS. 25 to 27. FIG. 25 shows the structure obtained through the process steps shown in FIGS. 15 to 19 in the conventional trench isolation method.
Prior to polishing the structure shown in FIG. 25 by CMP, a pre-etching is performed to selectively remove the flat area A1 of the silicon oxide film 5 as shown in FIG. 26.
Then the structure shown in FIG. 26 is polished by the CMP method to obtain a highly accurate trench isolation structure without residual 5a after polishing nor polished injuries 5b, as shown in FIG. 27.
However, the improved method shown in FIGS. 25 to 27 additionally requires a process of photolithography during pre-etching to improve the uniformity of CMP. This requires an increased number of process steps due to the additional mask for pre-etching, leading to an increase in the manufacturing cost.